As electronic devices become relatively smaller, packaging may become of particular interest. For example, a low-k interlayer dielectric (ILD) material may be used in place of a SiO2 ILD to reduce interconnect delay, for example.
The introduction of a low-K ILD material into silicon may impose new challenges for high wire density packaging. In particular, the inherently weak adhesion in the low-k interconnect makes the silicon more susceptible to a failure that may often be called ILD crack or delamination. ILD crack or delamination causes failure of the electronic device, which often happens during temperature cycling tests, for example. The technical article entitled, “Packaging Challenges in Low-k Silicon with Thermally Enhanced Ball Grid Array (TE-PBGA)”, EPTC 2010 by Tran et al. highlights the problems with a low-K ILD material.
As described in the Tran et al. technical article, one cause of the low-k failure has been determined to be the non-uniform distribution of mold compound fillers in the die corner opposite the mold gate. The drop-in heat spreader obstructs the mold compound flow during the transfer molding process, which resulted in greater filler loss in this corner.